GF(q) LDPC decoder design for FPGA implementation

Abstract

The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sup> ) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.