Abstract
The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC in order to cope with higher instantaneous luminosities and will switch to a 40 MHz readout rate using a trigger-less software based system. All front-end electronics will be replaced and several sub-detectors must be redesigned to cope with the higher detector occupancy and radiation damage. The current tracking detectors downstream of the LHCb dipole magnet will be replaced by the Scintillating Fibre (SciFi) Tracker. The SciFi Tracker will use scintillating fibres read out by Silicon Photomultipliers (SiPMs). State-of-the-art multi-channel SiPM arrays are being developed and a custom ASIC, called the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC), will be used to digitise the signals from the SiPMs. This article presents an overview of the R&D for the PACIFIC. It is a 64-channel ASIC implemented in 130 nm CMOS technology, aiming at a radiation tolerant design with a power consumption below 10 mW per channel. It interfaces directly with the SiPM anode through a current mode input, and provides a configurable non-linear 2-bit per channel digital output. The SiPM signal is acquired by a current conveyor and processed with a fast shaper and a gated integrator. The digitization is performed using a three threshold non-linear flash ADC operating at 40 MHz. Simulation and test results show the PACIFIC chip prototypes functioning well.
Highlights
: The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC
State-of-the-art multi-channel SiPM arrays are being developed and a custom ASIC, called the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC), will be used to digitise the signals from the SiPMs
The low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC) is a 64-channel ASIC implemented in 130 nm CMOS technology, aiming at a radiation tolerant design with a power consumption below 10 mW per channel
Summary
The front-end (FE) electronics provide the back-end with a digital representation of the position of the detected particles For this purpose, the modular system shown in figure 2a was developed, which is comprised of three elements: the analog board, the clusterization board and the master board. From the digital output of the analog board, the clusterization board FPGA performs additional processing of the PACIFIC output It computes the barycenter for each cluster of signals produced by a particle track, improving the resolution intrinsic to the geometrical layout of the sensors. The master board collects the data from the clusterization boards and send it through a fast communication link using the GBT chipset [6] and Versatile Link [7] devices. This board is equipped with DC/DC converters [8] to power the whole FE
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have