Abstract
Using oxide isolation, ISL gates can be fabricated without the relative slow lateral pnp transistor which is inevitable in pn-isolated processes. Now the clamping action is provided either by a fast vertical pnp only, or a reverse operated npn. Using a 1.2 µm thick epilayer and 3 µm minimum dimensions, propagation delay times of 0.7 ns are obtained at a current level of 200 µA per gate.
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