Oxidation-induced traps near SiO2/SiGe interface

Abstract

Using an Al/SiO2(wet)/Si0.9Ge0.1/n–Si/Al capacitor structure, effects of oxidation on bulk trap and interface states near the SiO2/SiGe interface are investigated. Two peaks at the energy levels of 0.23 eV (D1) and 0.40 eV (D2) below the conduction band edge are observed with the capacitance deep level transient spectroscopy (DLTS) method. The DLTS measurement results show a characteristic feature of interface states for the D1 peak. The interface state distribution obtained by the capacitance–voltage method also has a high density (6.9×1012/cm2 eV) peak at an energy level of 0.23 eV below the conduction band edge. The Si–O– dangling bonds are thought to be the source of the D1 peak. The annealing behaviors of the D2 peak show that D2 is a divacancy related bulk trap. The capture cross section and the trap density for the bulk trap D2 are 2.06×10−15/cm2 and 1.8×1014/cm3, respectively. The density of D2 is significantly reduced after low temperature postmetallization annealing.