Overvoltage Failure Process of Cascode GaN Field Effect Transistors

Abstract

The failure process caused by overvoltage stress in cascode GaN–field effect transistors (FETs) is discussed through single unclamped inductive switching (UIS) waveforms, burst UIS waveforms, and capacitance–voltage characteristic shifts. One of the critical disadvantages of GaN–high electron mobility transistors (HEMTs) is their lack of UIS withstand capability, primarily because there is no mechanism for removing holes generated by avalanche breakdown. The device failure is observed at the drain voltage peak in the single UIS, and sudden and random breaks are observed in the burst UIS even with the same overvoltage stress. Both hole and electron traps after the burst UIS are observed, and the failure position is at the chip edge. From these results, it is verified that cascode GaN–FETs are broken due to time‐dependent dielectric breakdown of passivation films.