Robustness of Cascode GaN HEMTs under Repetitive Overvoltage and Surge Energy Stresses

Abstract

Surge energy robustness is essential for power semiconductor devices in many power electronics applications, such as automotive powertrains and electrical grids. Si and SiC MOSFETs can dissipate surge energy via avalanche. However, GaN high-electron-mobility-transistor (HEMT) has no avalanche capability. Recent studies have investigated the surge energy robustness of p-gate GaN HEMTs, revealing a capacitive-charging-based withstanding process. The degradation of p-gate GaN HEMT under repetitive surge energy stresses has also been reported. This work, for the first time, studies the repetitive surge energy robustness of a 650-V rated cascode GaN HEMT in the unclamped inductive switching (UIS) test. The cascode GaN HEMT shows a lower failure boundary under the repetitive UIS stress than the one under the single UIS stress. When the surge energy approaches the repetitive failure boundary, devices do not fail immediately but within limited cycles of stress. Devices were found to survive 1 million UIS cycles when the peak UIS voltage is reduced to ~80% of the failure boundary, but show considerable parametric shifts after the repetitive stress, including an on-resistance (RDS(ON)) increase during both forward and reverse conductions, a reduction in the off-state drain leakage current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSS</inf> ), and a negative shift of the drain-to-source capacitance (C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> ). These behaviors of device failure and degradation under repetitive UIS stresses can be explained by the buffer trapping accumulation in GaN HEMTs, which may lead to a reduction of the device dynamic breakdown voltage. This physical explanation has also been validated by physics-based TCAD simulation.