Organic Damascene Process for 1.5-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m Panel-Scale Redistribution Layer Technology Using 5-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m-Thick Dry Film Photosensitive Dielectrics

Abstract

This paper presents a novel organic embedded trace damascene redistribution layer (RDL) process for panel-scale 2.5-D interposers and high-density fan-out package (HDFO) substrates. A minimum feature size of 1.5- $\mu \text{m}$ line and space using ultrathin polymer dielectrics on glass, silicon, and as well as on organic laminate was demonstrated. This is the first demonstration of a complete set of materials and processes that can be applied to large glass or organic panels, to bridge the interconnect gap between current semiadditive process (SAP) RDL and wafer back-end-of-line (BEOL) RDL. The ultra-fine pitch multilayer RDL structures demonstrated in this paper achieve an optimum balance of high IO density, high electrical performance, and low process costs. IO density in terms of IOs per mm per layer, as defined by Intel, refers to the number of traces routed per millimeter of die edge on one RDL layer of an interposer or package substrate. The current SAP technology can achieve an IO density of about 40 IOs/mm/layer on 510 mm $\times \,\, 510$ mm organic laminate panels. The challenges of fabricating copper metal traces below 5 $\mu \text{m}$ width and 5 $\mu \text{m}$ space using conventional SAP are discussed. On the other hand, wafer-based BEOL damascene RDL technology can scale to IO densities of greater than 200 IOs/mm/layer, but at relatively higher costs on 300-mm-diameter round wafers. An additional challenge for silicon interposers is low die-to-die interconnect data rate of single copper trace due to the high resistance of BEOL RDL structure. A combination of larger cross-sectional area with high aspect ratio (AR) is preferred for low-resistance, high-bandwidth escape routing traces. In this paper, the materials and process flow of embedded trace damascene RDL technology featuring trenches of 1.5 $\mu \text{m}$ width and 1.5 $\mu \text{m}$ space with AR of 2–4 will be described. A new 5- $\mu \text{m}$ -thick dry film photosensitive polymer dielectric IF4605 was used for the trench layer as well as the via layer. A large panel-scalable Surface Planar DFS8910 tool was used to achieve a highly planar metal–polymer RDL surface, at potentially lower costs than chemical-mechanical polishing that has been used in prior work. The processes discussed in this paper will enable routing of fine copper traces on panel-based interposers and HDFOs at higher throughput and potentially lower costs than BEOL processes. A two-metal layer, 20- $\mu \text{m}$ IO pitch silicon-like RDL test vehicle was fabricated with 2.5- $\mu \text{m}$ -wide and 2.5- $\mu \text{m}$ -space embedded traces and integrated with 2- $\mu \text{m}$ -diameter microvias using IF4605 on glass. There was no pad in the integration. This pad-less structure can be used for achieving theoretically maximum interconnect density. The process flow emulates the salient features of damascene processes used for BEOL RDL on semiconductor wafers, but simplifies them using dry film polymer materials and panel processes. Hence, it is referred to as organic embedded trace damascene or simplified as an organic damascene process (ODP) in this paper. The novel ODP interconnect addresses the current limitations of both SAP and BEOL processes. The key highlights of this new ODP technology are: 1) IO densities of 200 IO/mm/layer or more; 2) via-to-via pitch of $20~\mu \text{m}$ or less; 3) high AR of routing traces in the range of 2–4; 4) precise RDL linewidth control; 5) double-sided process with glass core; and 6) reduced number of process steps and panel-scalability leading to lower fabrication costs.