Via-in-Trench: A Revolutionary Panel-Based Package RDL Configuration Capable of 200-450 IO/mm/Layer, an Innovation for More-Than-Moore System Integration

Abstract

This paper presents, for the first time, a novel silicon damascene like via-in-trench (ViT) interconnect for panel-scale package redistribution layer (RDL) configuration. The panel scale damascene RDL in this paper comprises of ultra-fine copper embedded trenches and microvias with diameter equal to the width of trenches using a 5 µm thick dry film photosensitive dielectric. A 140 µm thick glass substrate is used as the core material. The new panel scalable ViT interconnect is targeted for low cost, next generation 2D and 2.5D interposers and high density packages. The ViT RDL is integrated with 2 µm diameter microvias with 2.5 µm half-line pitch copper traces embedded in a 5 µm thick dry film photo-imageable dielectric (PID) polymer. This RDL integration directly translates to IO density of 200 IO/mm/layer. IO/mm/layer, as defined by Intel, is the number of wires routed per mm of die edge on each layer of package substrate. There is no capture pad required for ViT interconnect demonstrated in this paper. The routing Cu trace is aligned directly on top of microvia instead of the conventional via-capture pad-trace interconnect configuration. The fabrication of such a high density RDL is achieved by patterning a trench over via and then fully filling with copper. Conventional i-line (365 nm) photolithography, widely used for patterning PWB and package substrates, was employed for fine trenches formation as well as small microvias in the PID. An advanced 5 µm thick PID film IF4605 was selected for build-up layers. Experimental results showed that microvias with diameters of 2 µm and trenches with half-line pitch of 2.5 µm were achieved in 5 µm thick IF dry film. Traces with half-line pitch of 1 µm were demonstrated in a 3 µm thick liquid photo resist film. The aspect ratios were 2.5 for dry film PID and 3 for liquid photo-resist respectively. The best interconnection density in terms of IO/mm/layer was calculated to be 200 using dry film PID and can be extended to 450 using thinner PIDs. For comparison, the IO density for state-of-the-art organic interposer was 40 by using semi-additive process (SAP). The embedded trench technology breaks through the limit of SAP and achieves 5-10X interconnect density compared to SAP. The ViT interconnect is a revolutionary package RDL configuration to meet the requirements of future package substrates for high performance computing, high bandwidth memory and micro-miniaturized system applications. The demonstration of ViT RDL configuration on thin glass substrate with L/S/Via/Pitch of 2.5/2.5/2/20 µm using embedded trench approach will be presented and the fabrication processes will be described in detail.