Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits

Abstract

In this paper, we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies, which minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results of two test circuits, a chain of inverters and a ripple carry adder, show that by using this sizing approach, the energy per operation can be reduced in more than 50% in a wide range of target performances. We use a 28-nm ultra-thin body and box fully depleted silicon-on-insulator technology and we show that the combination of supply voltage scaling, backplane biasing, and length biasing can be combined to obtain extremely robust (variability is almost halved) and energy efficient digital circuits. We also show simulation results for predictive technology models to show that the technique is also compatible with conventional bulk technologies.