Asymmetrical length biasing for energy efficient digital circuits

Abstract

In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.