Evaluation of Dual Mode Logic in 28nm FD-SOI technology

Abstract

For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technology, with the goal of improving energy efficiency for wide supply voltage operation range. By combining the operating characteristics of the DML and the extended body bias capability of the technology, energy efficient digital circuits that can effectively benefit from adaptive voltage and frequency scaling techniques can be defined. This manuscript reports evaluations of the DML against conventional static and dynamic CMOS logics for two benchmarks in the 0.3V-1V supply voltage range. First, a NAND-NOR chain was considered. Simulation results showed that the DML approach assures roughly the 40% savings in terms of energy consumption with respect to the static CMOS implementation and improves the speed about 20% in comparison to the dynamic CMOS design. Second, a 16-bit Carry Skip Adder was considered. Due to the unique capability of the DML to switch on-the-fly between static and dynamic modes of operation, an improvement of more than 20% in terms of EDP was obtained in comparison to the conventional CMOS adder design.