Optimization of the channel doping profile of vertical sub-100 nm MOSFETs

Abstract

Vertical transistors with channel lengths down to 30 nm were fabricated on the vertical sidewalls of mesas, which were produced by dry chemical etching of MBE grown layers. The electrical behaviour of transistors with planar doped barrier, using delta layers embedded in layers of intrinsic silicon, were investigated in comparison to transistors with conventional homogeneous channel doping. With planar doped barriers higher transconductances and thus higher electron velocities could be reached. In such devices with channel lengths below 100 nm distinct velocity overshoot occurred even at room temperature. The influence of the position of the delta doping in the channel on the electrical parameters of planar doped barrier FETs was experimentally investigated.