50-nm vertical sidewall transistors with high channel doping concentrations

Abstract

Vertical MOSFETs have been proposed in the roadmap of semiconductors as a candidate for sub 100 nm CMOS technologies. A process flow using sidewall gates and implantations instead of multiple layer depositions reduces process complexity and offers better CMOS compatibility. High doping concentrations in the channel are needed for sub 100 nm devices. Especially for vertical transistors the uniform channel doping is more critical than for a planar technology, where optimized profiles can be easier implemented. Therefore, we investigated for the first time vertical MOSFETs with high channel doping concentration up to 1*10/sup 19/ cm/sup -3/ and channel lengths down to 50 nm. The impact of the high doping levels on threshold voltage and on tunneling currents is discussed. Finally, by using slight process modifications first results on vertical double gate MOSFETs will be presented, which in principle can operate with an undoped channel region.