Optimization of Monolithic 3D TSV Transformers for High-Voltage Digital Isolators

Abstract

In this paper, 3D TSV transformers are designed and fabricated for monolithic high-voltage digital isolator applications. The transformers are embedded in the bottom layer of a silicon substrate by using through-silicon-via (TSV) technique without consuming chip surface area, and sandwiched between system circuitries using flip-chip bonding technique for reducing form factor. For a transformer with a size of 1.4 mm × 1.4 mm, a peak primary quality factor of 12.7 and a voltage gain of 0.82 at 34.1 MHz are experimentally demonstrated. Moreover, the performance dependent on the various design parameters is also investigated, including coil sizes, number of winding turns, and coil shapes. Experimental results illustrate the design flexibility of the proposed transformer technology, which allows tradeoffs among key electrical properties such as peak quality factor, mutual inductance, voltage gain, and operating frequency. Asymmetric transformers with different number of turns for the primary and secondary coils are also demonstrated. They can achieve a voltage gain around unity, but sacrifice the bidirectional signal transfer capability.