OPTIMIZATION OF EMBEDDED CONTROLLERS BASED ON REDUNDANT TRANSITION REMOVAL AND FAULT SIMULATION USING K-WISE TESTS

Abstract

This paper presents an efficient redundancy removal technique for hierarchical optimization of FSM networks. In this technique, we first remove redundant transitions from the state transition graph (STG) of the driven FSM, M2, of the cascaded network by applying a reachability analysis to the composite machine, M1 → M2, once and for all. Then, a k-wise complete test suite for M2 is generated from the new STG of the driven FSM. Redundancy identification consists of two phases. In the first phase, almost all of the detectable stuck-at faults are identified by fault simulation using the k-wise test suite. During the second phase, each fault f that is undetected by k-wise tests is injected in M2 to obtain [Formula: see text] in the topologically sorted order one by one. Then the equivalence check of two FSMs M2 and [Formula: see text] in the environment where [Formula: see text] is driven by M1 is done. If a fault is found to be undetectable in the second phase, it is a redundant fault and kept in M2 ([Formula: see text] is taken as M2). Finally, simultaneous removal of redundant faults is done at logic level. We present experimental results to provide a comparison of the data produced by the state-of-the-art FSM network optimizer and show the effectiveness of our approach.