Test generation for redundant faults in combinational circuits by using delay effects

Abstract

Practical combinational circuits include some undetectable stuck-at faults called the redundant faults. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, we study the testing problem of the redundant fault in the combinational circuit by using delay effects and propose a method for generating a test-pair of a redundant fault. By using an extended seven-valued calculus, the proposed method generates a dynamically sensitizable path which includes a target redundant fault on a restricted single path. The dynamically sensitizable path will propagate the effect of the target redundant fault to the output of the circuit by the delay effects. Preliminary experiments on the benchmark circuits show that test-pairs for some redundant faults are generated theoretically. >