Optimization of Cu protrusion of wafer-to-wafer hybrid bonding for HBM packages application

Abstract

This work focuses on the effect of Cu protrusion on the reliability of High Bandwidth Memory (HBM) fabricated by wafer-to-wafer hybrid bonding (W2W-HB) process. The thermal stress induced by large coefficient of thermal expansion (CTE) mismatch between different materials could seriously deteriorate the device performance, and even lead to failure. Different manufacturing and service conditions could greatly affect the microstructure and deformation behavior of the through silicon via (TSV). In this paper, a new process was designed to realize the self-compensation of the surface topology by rationally utilizing the dishing defects caused by CMP. The influence of dielectric materials (dielectric layer thickness and CTE) on Cu protrusion height was systematically explored. A finite element analysis (FEA) model was proposed to provide insight into the Cu protrusion mechanism under different operating conditions. Annealing tests were carried out to identify how the microstructure affects protrusion and to verify the accuracy of the model. During the test, the extruded TSV was observed using scanning electron microscopy (SEM) and atomic force microscopy (AFM). Mechanisms of Cu protrusion in TSVs during heat treatment were analyzed, and possible factors involving thermal stress were discussed through the model. In addition, debonding risk was evaluated by comparing the peak interfacial peeling stress and the protrusion height for various scenarios. The conclusions can be used to understand and solve the key issues in the reliability challenges of HBM W2W-HB stacking process by enabling high-throughput TSV fabrication.