Optimal Sprinting Pattern in Thermal Constrained CMPs

Abstract

As studied in literatures, Computational Sprinting (CS) is a promising technique to tackle the thermal challenge for Chip Multi-Processors (CMPs) in dark silicon era. Sprinting pattern, the boosted chip and voltage during the sprinting time, greatly impacts the CMP performance. In the paper, we address how to find out the optimal sprinting pattern which maximizes the performance of CMPs within thermal limitation. First, we conduce a mathematical proof to show that any thermal-constrained CMP, when it executes an application, has a specialized, sustainable configuration (v <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> , f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ), under which the CMP can keep sprinting without resting and meanwhile its performance is maximized. Then, we design a self-adaptive algorithm automatically altering the chip frequency with adjustable step size and voltage in runtime to reach the optimal value. Finally, our extensive experimental results reveal that our Optimal Sprinting Pattern (OSP) outperforms state-of-the-art sprinting techniques, Full Sprinting Policy (FSP) and Adaptive Sprinting Pacing (ASP). Specifically, our OSP improves the computational efficiency in MIPS by up to 59 percent against FSP and 40 percent against ASP. It also achieves higher energy efficiency in MIPJ, by up to 41 and 25 percent over FSP and ASP, respectively. Moreover, we demonstrate that our method is effective for various CMPs with different scales, CPU architectures and chip nano-technologies.