Revisiting Processor Allocation and Application Mapping in Future CMPs in Dark Silicon Era

Abstract

Abstract With technology advances and the emergence of new fabrication and VLSI technologies, current and future chip multiprocessors (CMPs) are expected to have tens to hundreds of processing elements and Gigabytes of on-chip caches, which are connected by a high bandwidth network-on-chip (NoC). Unfortunately, due to limited power budget of a computing system, specially for its processing element(s), it is impossible to keep all cores, caches, and network elements working at highest voltage level—that would resulted in dark silicon computing era, where by employing system-level or architecture-level techniques, one can keep a great portion of a CMP elements OFF (or in dim mode) to meet the power budget of the system while the system still delivers a high-performance computation. In this work, we first describe the importance of NoC design and management in delivering high-performance computation in a dark silicon-based CMP platform—we propose a novel highly scalable NoC architecture and its required management policies in order to support turning some routers/links/buffers OFF while guaranteeing that it delivers the bandwidth needs of the running application(s). Then, by employing the introduced NoC architecture, we propose to revisit the processor allocation strategy and application-to-core mapping algorithm in order to make maximum use of the provided NoC bandwidth and capability while meeting the power and performance goals of the hardware platform and application, respectively. Our extensive simulation results of a 64-core CMP model show that the proposed algorithms are able to improve the system performance by 10%–50% when running multithreaded applications.