Abstract
With the increase in the number of cores in processor chips observed in recent years, design choices—such as the number of cores in chip, the amount of resources per core, and whether to design homogeneous or heterogeneous chips—need to be given proper support. Several studies on heterogeneous multi-core processors are concerned with performance improvements. In this work, we propose mathematical models to analyze some of these design issues with focus on the reduction of processor dynamic energy. In particular, these models allow the comparison of the dynamic-energy consumption of multi-core architectures when they execute a workload in the same amount of time while allowing different core operating frequency between the compared architectures. The results of the analysis allow chip designers to choose the right conditions for optimal energy savings in heterogeneous multi-core chips based on the parallel fraction of the workloads and on the distributions of the resources among the cores in the chip. Under a simplified context, the devised models agree with the consolidated knowledge that heterogeneous multi-core chips have considerable advantage over homogeneous multi-core and single-core architectures in terms of energy efficiency.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
