Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core Processors

Abstract

Heterogeneous Multi-core Processor (HMP) is a set of cores exposing the same instruction set architecture (ISA). The cores in HMPs can differ relative to performance, area, power, and micro-architecture design. Many researchers have investigated HMPs as an alternative to optimize the relationship between power consumption and performance. Usually, the researchers use homogeneous multi-core architectures and emulate the heterogeneity through Dynamic Voltage Frequency Scaling (DVFS). In this paper, the goal is to investigate the benefits of using different cache sizes in HMPs and how a scheduler can exploit such benefits according to the system's workload. In this initial study, we have used an FPGA to generate multi-core architectures with different cache sizes to execute some applications in both heterogeneous and homogeneous multi-core processors. Then, a prototype of a scheduler was implemented to do the thread assignment based on offline profiling. For the best static scheduling, the overall cache miss rate was lower on the HMP using an amount of 15KB of cache than on a homogeneous multi-core processor using an amount of 16KB of cache.