Optimal on-chip cache hierarchy synthesis with scaling of technology

Abstract

With the ever widening disparity between processor speed and main memory speed and the increasing availability of integration and die-area, cache hierarchy design plays a central role in processor performance. Previous on-chip caches have been area limited, but with technology scaling, on-chip caches are becoming both area and latency limited. With scaling of technology and evolving of applications, the optimal configuration of future on-chip cache in microprocessors is an interesting question. To answer this question we combine analytical performance models and scalable physical models for latency and area as well as trace simulation results into a high level synthesis tool-CacheOpt. CacheOpt automates the synthesis of an optimal cache hierarchy under area, I/O, and latency constraints with respect to a given technology and application batch. We investigate three configurations of cache hierarchy-PC (primary cache on chip), PC/SC (primary cache on-chip, secondary cache off-chip), and PC/SCOC (primary and secondary cache on-chip) across a wide range of cache size, line size, and set size combinations and propose optimal cache hierarchies for technologies from 0.7 /spl mu/ to 0.1 /spl mu/.