On-the-fly speed and power scaling of an E-TSPC dual modulus prescaler using forward body bias in 0.25 μm CMOS

Abstract

An extended true-single-phase-clock (E-TSPC) dual-modulus prescaler with a division ratio of 2 and 3 employs the forward body biasing (FBB) technique for achieving efficient on-the-fly speed and power control. The circuit is implemented in 0.25 urn CMOS. With the forward body bias voltage of 0.7 V applied to N- and P-FET's, the maximum operating frequency is improved by 80 and 87 % in the divide-by-2 and −3 modes, respectively, while the current dissipation is increased by 27 and 28 % As a result, the figure-of-merit of the prescaler is enhanced by 42 and 46 % for the divide-by-2 and 3 modes, respectively. The phase noise however does not show significant degradation at the FBB voltage less than 0.7 V. We believe that the FBB technique can be an efficient means of on-the-fly speed and power scaling in CMOS RF E-TSPC prescaler circuits.