An E-TSPC Divide-by-2 Circuit With Forward Body Biasing in 0.25 $\mu$m CMOS

Abstract

A forward body biasing (FBB) technique is employed by an extended true-single-phase-clock (E-TSPC) divide-by-2 circuit in 0.25 mu m CMOS for an efficient on-chip control of power and speed. By applying the forward body bias voltage of 0.4 V, the maximum operating frequency is improved by 78% while the current dissipation is increased only by 21%. As a result, the divider figure-of-merit is improved by 46%. The phase noise however is not significantly affected by the forward body biasing. We believe that the FBB technique can be an efficient means for on-chip scaling of speed and power in E-TSPC RF frequency divider circuits.