Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

Teijo Lehtonen,Juha Plosila,Pasi Liljeberg

doi:10.1155/2007/94676

Teijo Lehtonen, Juha Plosila + Show 1 more

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https://doi.org/10.1155/2007/94676

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Abstract

We propose link structures for NoC that have properties for tolerating efficiently transient, intermittent, and permanent errors. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. The protection against transient errors is realized using Hamming coding and interleaving for error detection and retransmission as the recovery method. We introduce two approaches for tackling the intermittent and permanent errors. In the first approach, spare wires are introduced together with reconfiguration circuitry. The other approach uses time redundancy, the transmission is split into two parts, where the data is doubled. In both structures the presence of permanent or intermittent errors is monitored by analyzing previous error syndromes. The links are based on self-timed signaling in which the handshake signals are protected using triple modular redundancy. We present the structures, operation, and designs for the different components of the links. The fault tolerance properties are analyzed using a fault model containing temporary, intermittent, and permanent faults that occur both as bursts and as single faults. The results show a considerable enhancement in the fault tolerance at the cost of performance and area, and with only a slight increase in power consumption.

Highlights

The move towards nanoscale circuits increases performance and capacities of ICs, but poses new challenges to circuit design
For tolerating permanent and intermittent errors we introduce two methods, one that uses hardware redundancy and the other based on time redundancy
We extend the model by assuming that a fault affects its neighbouring wires in both directions with a certain probability p1, two neighboring wires with probability p2 and so on

Summary

Introduction

The move towards nanoscale circuits increases performance and capacities of ICs, but poses new challenges to circuit design. As the dimensions shrink dramatically, it is becoming increasingly difficult to control the variance of physical parameters in the manufacturing process. This results in faults and decreased yield which increases the costs per functioning chip [1, 2]. An NoC system consists of many processing blocks which have different timing requirements and can operate at different clock frequencies. Communication between these blocks needs synchronization which is error-prone. A viable solution for this is the use of the VLSI Design Transmitter req req ack ack nack reconf Data 20 ctrl 84 Data.

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