Abstract
Modern high-performance SoCs contain many IP cores such as processors and memories. NoCs have been proposed as a scalable interconnect solution to integrate large multiprocessor SoCs [BM02, PGI+05]. Having a large SoC with complex communication among its cores, the complete verification coverage at pre-silicon stage is almost impossible. Therefore in addition to electrical bugs, some design bugs may also appear in the final prototype of an SoC.
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