One instruction set computer with optimised polarity‐tunable model of double gate CNTFETs

Abstract

Emerging devices such as double gate carbon nanotube field effect transistors (DG CNTFETs) have opened up manifold possibilities for reconfigurable logic design. The thickness of gate oxide and the employment of inhomogeneous dielectrics over and under the carbon nanotubes (CNTs) impact the operation of DG CNTFETs. In this work, the dielectric constant and the thickness of the gate oxide are optimised to suppress the ambipolar conduction in CNTFETs. A multi-objective genetic algorithm-based approach is proposed to optimise these parameters. The contributions in this study are two-fold: firstly, a DG CNTFET is fabricated with the optimised parameters. By exploiting the ability to select the conduction behaviour using a second gate in the fabricated DG CNTFETs, the device is electrostatically programmed to behave as an n or p-type CNTFET. Secondly, a one instruction set computer is simulated with the optimised model of DG CNTFET. A universal static logic cell which implements 16 logic functions, a D-Latch and a D-FF were built with DG CNTFETs. The logic circuits with polarity-tunable DG CNTFETs outperform other logic structures. There is a 40% betterment in performance primarily due to the reduced number of logic levels and by 25% due to the reduced delay.