On-Chip S-Shaped Rat-Race Balun for Millimeter-Wave Band Using Wafer-Level Chip-Size Package Process

Abstract

In millimeter-wave CMOS circuits, a balun is useful for connecting off-chip single-end devices and on-chip differential circuits to improve noise immunity. However, an on-chip balun occupies large chip area. To reduce the chip area required for the on-chip balun, a new rat-race balun using rewiring technology with a wafer-level chip-size package (W-CSP) is proposed. The W-CSP balun occupies no area in a die because it is placed over integrated circuits. In the proposed balun, an S-shaped structure is adopted in order to directly connect the balun to differential GSGSG pads on a chip with small area. The S-shaped W-CSP balun was fabricated on a silicon-on-insulator (SOI) substrate. The core area of the S-shaped rat-race balun is 480 mum times 735 mum, which is 22.4% that of a square rat-race balun. As a result of measurement, we found that the minimum insertion loss is 1.7 dB and the operating frequency range is 40 to 61 GHz.