Wafer level and substrate level chip scale packaging

Abstract

Wafer level chip scale packaging (CSP) is gaining more momentum as a low cost, high performance solution for portable products. The design demands for portable products is particularly difficult since the designer must find solutions that provide a smaller footprint and higher performance, but at the same time must be cost competitive with current packaging offerings. To date, the fine pitch BGA style of chip scale packages have not offered the cost needed for these low I/O products. The wafer level CSPs do provide the cost advantage with the promise of continued cost reduction in the future. There are a number of different wafer level CSPs currently in the market. This paper addresses wafer level CSP development for integrated passives developed for both silicon wafers and large area glass panels (350 mm/spl times/400 mm).