Encapsulated water level chip scale package (eWLCSP™) for cost effective and robust solutions in FlexLine™

Abstract

The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced tremendous growth due to the surge in demand for advanced mobile products and pressure of cost reduction. The increased demand is seen for both 200mm wafers and 300mm wafers, however a significant segment of the market continues to be driven by 200mm designs. The infrastructure capacity supporting 200mm WLCSP has been stressed as a result of the mature status of 200mm technology and the rate of conversion of alternative package formats to WLCSP. This creates a dilemma for WLP service providers because adding 200mm capacity continues to require a significant amount of capital. Since 200mm volumes will most likely decline within the next 5 years, it is difficult to justify the use of capital when the depreciation term is longer than the anticipated life cycle of the product. Typically, Si WLCSP package is conducted with full function test at wafer level sorting and followed by mechanical blade dicing with or without laser grooving. Mechanical blade dicing may cause front side chipping and backside chipping, which in turn will cause package failures that are not detected before the SMT process. The surge in demand on WLCSP makes the industry realize the potential failures, and the need to actively look for a solution. While conventional backside processes can address backside chipping, it can't provide protection from the sidewall cracking. This is motivating the industry to look into 5-side inspection in the tape and reel (TnR) process, although this obviuously increases the package cost while not necessarily screening out the failure units due to no functional test being applied. This paper introduces a new encapsulated WLCSP product (eWLCSP™) and innovative manufacturing process known as the FlexLine™. The new eWLCSP product has a thin protective coating applied to at least 4 sides of the silicon sidewall with the optional to encapsulate all exposed silicon surfaces on the die. The applied coating protects the silicon and fragile dielectrics and prevents handling damage during dicing and assembly operations, effectively providing a durable packaged part in the form factor of a WLCSP. The FlexLine manufacturing process used to produce eWLCSP leverages existing high volume manufacturing methods with exceptionally high process yields. In this process the silicon wafer is diced prior to the wafer level packaging process. The dice are then reconstituted into a new wafer form with adequate distance between the die to allow for a thin layer of protective coating to remain after final singulation. Standard methods are used to apply dielectrics, thin film metals, and solder bumps. The resulting structure is identical to a conventional WLCSP product with the addition of the protective sidewall coating. The most important step of the process is when the diced Si die go through a kind of burn-in test after running through the whole FlexLine assembly process before final wafer level test. In package singulation, there is no additional mechanical or thermal damage on either front side or sidewall/backside of Si die due to the protection of the encapsulant. The singulated package becomes the real known good die without the need to conduct a manual 5-sided inspection. This paper discusses the key attributes of the new eWLCSP as well as the manufacturing process used to create it. Reliability data will be presented and compared to conventional WLCSP products and improvements in package reliability and performance will be discussed and compared to conventional WLCSP.