Sidewall Protection for a Wafer Level Chip Scale Package

Abstract

Wafer Level Chip Scale Package (WLCSP) is widely used in portable electronic products like mobile phones, tablets, digital cameras and etc. WLCSP technology is driven by cost, size, and ease of testing and is an ideal solution to package low to middle I/O chips. The main issue of WLCSP is silicon and fragile dielectric crack at the die edge due to an unpackaged die. WLCSP handling defects can occur at any step across the device process flow from WLCSP backend process including dicing, tape and reel packing to the final surface mount of the WLCSP onto the product PCB. The crack at the die edge can diminish the integrity and reliability of the integrated circuit (IC). Die sidewall protection becomes even more critical as silicon nodes scale beyond 22nm to 14nm and 10nm, where the risk of potential sidewall damage intensifies due to the brittle dielectrics. In this work, we have developed a sidewall protection wafer level chip scale package, which leverages the existing manufacturing method of wafer level fan out package and classical WLCSP technology. In the process flow, the wafer is diced, picked and placed on the carrier with adequate distance between the die prior to the wafer molding process. The dies are reconstructed into 300mm molded wafer and then go through the wafer level packaging process. The tested known good dies (KGDs) are surrounded by epoxy molding compound (EMC), a non-brittle material, which prevents damage to the die itself. In this work, we have developed 5mm × 5mm sidewall protection WLCSP with 196 I/O (14 × 14 full array pattern). Pitch is 0.35mm and solder ball size is 200um. Daisy chain WLCSP structure with SAC105Ni solder ball is used. Both board level thermal cycling test and drop test are carried out for this package reliability test. Cu RDL contact resistance is also discussed