Thermal management for wafer level packaging (WLP)

Abstract

In this study, the thermal performance of wafer level packaging (WLP) in still air environments is characterized with thermal measurements. Thermal test dice with built-in heaters and temperature sensors are used. Effects of WLP size, WLP design, power dissipation (Pd) area on die, and heat spreaders are investigated. Temperature sensors at different die locations are used to map the die temperature. WLP and board resistance contributions to the overall thermal resistance are also assessed. It is found that WLP package resistance is only a small portion of total junction to ambient thermal resistance. The heat spreading capability of the PCB significantly affects the overall thermal resistance. WLP design details do not make a significant difference since heat spreading in WLP is carried out in Si. Small WLP has higher thermal resistance. Small Pd area results in higher thermal resistance. Furthermore, localized heating causes “hot spots”. Heat spreaders can enhance the thermal performance.