Abstract
This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. Test escapes may take place while testing faults in the memristors. Therefore, two solutions are proposed to obtain full coverage for the MRL NAND and NOR gates. The first is to apply scaled input voltages and the second is to change the switching threshold of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs.
Highlights
Over the past decades, semiconductor technology has provided enormous enhancements in systems characteristics such as power consumption, speed, reliability and production cost
It is proven that three ordered test vectors are needed for full coverage in Memristor Ratioed Logic (MRL) NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs
For the NAND logic gate, consider for example, the fault R1 stuck at Roff; it is clear from Figure 3 that all test vectors produce the correct output except the test vector AB = 01
Summary
Semiconductor technology has provided enormous enhancements in systems characteristics such as power consumption, speed, reliability and production cost. (2016) On the Production Testing of Memristor Ratioed Logic (MRL) Gates. In the AND logic gate, when the current flows into the memristors, the resistance of the memristors increases and reaches Roff eventually. In the AND logic gate, consider the input vector AB = 10 The current flows into the memristor labeled R2 in Figure 2(a) and R2 reaches Ron towards the end of the logic evaluation. The resistance of the memristors behave in the exact opposite way of the AND logic gate and the output voltage Vout,OR is . Memristive devices lack signal restoration, i.e., the output voltage levels will degrade if these logic gates are cascaded for several levels [1]
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