A Testability Enhancement Method for the Memristor Ratioed Logic Circuits

Abstract

The Resistive Random Access Memory (RRAM) is a two-terminal variable resistance device, and the memristor ratioed logic (MRL) is a hybrid RRAM-CMOS style of logic circuit. The MRL AND and OR gates are implemented by the RRAM devices, and the MRL NOT gate is implemented by the CMOS inverter. However, the MRL circuits are prone to test escape. This work proposes a method to improve the testability of MRL circuits by replacing the CMOS inverters with the FinFET inverters. The test escape problem is solved by adjusting the switching threshold voltages of the FinFET inverters, and it is implemented by selecting the FinFET inverters in different operation modes. In Addition, some equivalent relationships in the fault set of the improved MRL gates are discovered. These fault equivalences of MRL gates result in a fault collapse ratio of about 50%. The test patterns for the production test of the improved MRL circuits can be generated by the traditional ATPG method. The test results of some typical MRL circuits obtained from the commercial ATPG tool show that the proposed method is able to achieve 100% fault coverage and at least 55% fault collapse ratio.