Abstract
Multiple-valued logic systems have been considered as a solution for the challenges of the nanoscale binary very large scale integration chips. However, the main concerns about these systems are the noise impacts, especially in the presence of process and temperature variations. In this study, the impacts of process and temperature variations on the crosstalk effects in multiwall carbon nanotube (MWCNT) bundle interconnects in ternary systems are investigated. The deviation in the worst-case crosstalk delay, noise, and the power introduced by the process variations are investigated using comprehensive Monte Carlo simulations. Also, analyses are conducted for the global level interconnects at 22 nm technology node for repeated MWCNT bundle interconnects. The results indicate that the average deviations in the worst-case crosstalk delay and crosstalk noise area in the presence of all sources of process variations in the repeated MWCNT bundle interconnects are about 14%. In addition, the maximum variations in the lumped resistance, distributed resistance, kinetic inductance, electrostatic capacitance, coupling capacitance and quantum capacitance of the MWCNT bundle interconnects in ternary systems in the presence of all sources of process variations are 4.6%, 14%, 7.2%, 8.2%, 5.1%, and 5.6%, respectively. According to the results, higher temperature increases the resistance of the MWCNT bundle interconnects and thereby the crosstalk delay and crosstalk noise area mainly due to the reduction of the mean free path of the MWCNTs in a bundle.
Published Version
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