Abstract
The paper presents synthesis process of a hardware implemented reconfigurable logic controller from a ladder diagram according to IEC61131-3 requirements. It is focused on the originally developed a high-performance LD processing method. It is able to process a set of diagrams restricted to logic operations in a single clock cycle independently from the number of processed rungs. The paper considers the compilation of the ladder diagram into an intermediate form suitable for logic synthesis process according to developed processing method. The enhanced data flow graph (EDFG) has been developed for the intermediate representation of an LD program. The original construction of the EDFG with attributed edges has been described. It allows for efficient representation and processing of logic and arithmetic formulas. The set of compilation algorithms that allow to preserve serial analysis order and to obtain massively parallel processing unit are presented. The overview of a hardware mapping concludes the presented considerations.
Highlights
The Programmable Logic Controllers (PLC) have been used since 1970s and first they were applied to relay control systems
The proposed method of implementation has been compared with direct enhanced data flow graph (EDFG) mapping approach
The Spartan II and the Spartan 3 are equipped with 4 input LUTs while the Spartan 3 is equipped with combinatorial 18x18 multipliers
Summary
The Programmable Logic Controllers (PLC) have been used since 1970s and first they were applied to relay control systems. Within years of fast development of electronic technology, the requirements given to PLC become higher all the time (operating speed, handling of analog objects, the increasing reliability, etc.). The areas of PLC applications include small complexity processes as well as large manufacturing lines. An intermediate form of the control program has been developed according to considered standard requirements. Algorithms, presented in this paper, are a part of the developed concept of reconfigurable logic controllers families and toolset for their programming according to the IEC61131-3 reference manual
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