On Translation of LD, IL and SFC Given According to IEC-61131 for Hardware Synthesis of Reconfigurable Logic Controller

Abstract

The paper presents developed synthesis methodology of a hardware implemented reconfigurable logic controller from multiple languages incorporating ladder diagrams, instruction list and sequential functional chart according to IEC61131-3. It is focused on the originally developed a high performance computation model based on properly defined variable access. The method address synthesis process of logic and arithmetic operations. Presented approach is able to synthesize not only basic constructs of languages but also complex modules like timers and counters. The paper acquaint with the compilation of considered languages and complex modules into intermediate form suitable for logic synthesis process according to developed analysis, translation and mapping methods. The data flow graph has been chosen for intermediate representation of a program. An original enhancement of the DFG with attributed edges and specific nodes has been described. It allows for efficient representation and processing of logic and arithmetic formulas. The set of compilation algorithms that preserve effects of serial execution order and offer obtaining massively parallel processing unit are presented.