Abstract
The paper presents the synthesis and implementation algorithms of reconfigurable logic controller (RLC) implemented in a FPGA. In opposite to software centric PLCs, the RLC utilize massively parallel hardware execution of control algorithms. The specific hardware implementation significantly reduces the throughput time. The input program is described by the SFC given according to IEC61131-3 standard. An original intermediate representation with use of data flow graph has been developed for program representation and synthesis purposes. The algorithm of creating graph representation maintains sequential dependencies of processing and reveals parallel tasks. Developed method of scheduling and mapping is dedicated for implementation in LUT based FPGA devices. There are considered direct mapping based on greedy approach and optimized methods that are FPGA architecture aware. The paper is concluded with exemplary implementation comparison.
Published Version
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