Abstract
Network-on-Chip (NoC) built upon metal low-k interconnect wires, are to meet the ever stringent performance requirements in the future technology nodes. In response to this interconnection crisis, the wireless network-on-chip (WNoC), enabled by the availability of miniaturized on-chip antennas and transceivers, is envisioned one of the most revolutionary promising approach alternatives. In this paper, we present a new WNoC architecture with a layered topology, where a metal/low-k based wired network is partitioned into several subnetworks, and these subnetworks are connected through a wireless network that is overlaid on top of them. Due to limited transmission range, the wireless nodes in the wireless network actually communicate with each other in a multiple-hop fashion. As a large volume of traffic will go through the wireless nodes, a contention avoidance routing algorithm is adopted. In addition, two virtual channels have been introduced into the wireless router design to avoid any possible deadlocks that otherwise may occur. Experiment results have shown that throughput of the proposed architecture, on average, is about 20% higher than that of the existing WNoC architectures. And delay of the proposed architecture is about 30% less than the existing WNoC architectures.
Highlights
Network-on-Chip(NoC) has emerged as a communication backbone to enable a high degree of integration in multi-core System-on-Chips (SoCs) [1]
The long distance packets are routed through wireless mesh, while the short distance packets can only be transferred through the wired mesh
We have proposed a new wireless network-on-chip (WNoC) structure, its routing algorithm, and correspondingly, the design of the wireless router
Summary
Network-on-Chip(NoC) has emerged as a communication backbone to enable a high degree of integration in multi-core System-on-Chips (SoCs) [1]. Conventional NoCs rely on multi-hop packet-switched communications, where a data packet needs to pass through a series of routers/switches with considerable power and latency implications To overcome these problems, express virtual channels are introduced to various NoC architectures [2~6] that can improve NoC’s power, latency and throughput performance [2]. The overheads of a wireless link may not be justifiable for 1 mm range of on-chip communication as compared to a wired channel In light of these technology advancements, the latest research is geared towards the mixed WNoC architectures which employ wired links between adjacent nodes and use one-hop or multi-hop wireless links between a few selected distant nodes [9][10][8].
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