Abstract
Typical 3D integrated circuit structures based on through-silicon vias (TSVs) are complicated to study and analyze. Therefore, it seems important to find some methods to investigate them. In this paper, a method is proposed to model and compute the time-domain coupling noise in 3D Integrated Circuit (3D-IC) based on TSVs. It is based on the numerical inversion Laplace transform (NILT) method and the chain matrices. The method is validated using some experimental results and the Pspice and Matlab tools. The results confirm the effectiveness of the proposed technique and the noise is analyzed in several cases. It is found that TSV noise coupling is affected by different factors such as source characteristics, horizontal interconnections, and the type of Inputs and Outputs (I/O) drivers.
Highlights
Over the last four decades, silicon semiconductor technology has advanced at exponential rates in terms of performance and productivity [1,2]
It is found that through-silicon vias (TSVs) noise coupling is affected by different factors such as source characteristics, horizontal interconnections, and the type of Inputs and Outputs (I/O) drivers
A trapezoidal signal switching from 0 to 1.8 V with a rising/falling time of 10 ps and for lRDL = 200 μm and lRDL = 500 μm. These results present the TSV noise coupling without the coupling a source resistance of 50 Ω at frequency 1 GHz was used, Z and Z were replaced by resistances of among the redistribution layers (RDLs)
Summary
Over the last four decades, silicon semiconductor technology has advanced at exponential rates in terms of performance and productivity [1,2]. Materials, devices, circuits, and system limits discloses that silicon technology still has colossal potential for achieving terascale integration (TSI) of a significant number of transistors per chip. Such large-scale integration is feasible by assuming the development and bulk economic production of metal-oxide-semiconductor double-gate field-effect transistors. The second consists of developing high-performance technologies for interconnections between chips (SiP). Since the interconnections are required in electronic systems, the number of interconnections cannot be decreased adversely to the area which can be reduced using 3D technology based on vertical interconnections
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