Novel polysilicon gate engineering with a laser thermal process for sub-40 nm CMOS devices

Abstract

We demonstrate a novel poly-Si gate engineering by laser thermal process (LTP) to suppress gate depletion for high performance sub-40 nm CMOS devices. To show the full advantage of LTP, an optimized BEOL process has been employed to suppress dopant deactivation and achieve a reduction of electrical inversion gate oxide thickness by 0.1/0.06 nm (PMOS/NMOS), which improves the I on current by 11/7% (PMOS/NMOS). Furthermore, a novel source-drain rapid thermal annealing (SD-RTA) has been developed to suppress dopant dose loss to achieve a 5% improvement of the I on current for NMOS.