Novel phase‐locked loop with digital control techniques

Abstract

AbstractRecently, a number of digital phase‐locked loops (DPLL) have been studied. In the usual DPLLs, a divider is added to the output so that the discontinuous and sudden variations in the frequency and phase adjustment by digital operations can be averaged and smoothed. Hence, in the usual DPLLs, an internal clock oscillator with its frequency several tens times the input frequency is needed. This requirement places a certain limit in the input frequency by the maximum operating frequency of the digital logic circuit if the DPLL is used for a high input frequency.This paper proposes a phase‐locked loop (DC‐PLL) in which no divider is used and a clock frequency is almost equal to that of the input signal used for digital control. The free running frequency of the loop is equal to the clock frequency. The waveform of the clock signal is transformed to a saw‐toothed signal and the content of the reversible counter is transformed to a dc signal by a D‐A converter.These two signals are injected simultaneously to the voltage comparator so that the comparator outputs at the moment the former exceeds the latter. This is the output signal of the system.By the phase control signal, the content of the reversible counter varies and the output dc level of the D‐A converter also varies. At the same time, the phase of the output signal changes so that the phase control is accomplished. The characteristics of the proposed phase‐locked loop are confirmed to be identical to those of the conventional DPLL in which a divider is used.