A novel digital PLL with good performance and very small area

Abstract

A novel digital PLL(Phase Locked Loop) is presented in this paper. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and cycle control to digitally control the DCO(Digitally Controlled Oscillator) output clock frequency, so as to get wider frequency range and smaller jitter. This PLL uses NAND gate as the basic delay cell, which can completely reset DCO in a very short time, and prevent the jitter accumulation. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65nmG process. Its chip area is only 5255μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , DCO's frequency have a wide range between 550MHz to 2.45GHz. Its total power is around 1.0mW when DCO's frequency is 1.0GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is smaller than 40ps.