High‐speed digital PLL using trigger oscillators

Abstract

AbstractThe conventional digital phase‐locked loop (DPLL) cannot be used for high‐frequency purposes, because the local oscillator frequency of the DPLL is several times the input frequency. This paper proposes a use of trigger oscillators to the DPLL. The first‐ and second‐order DPLL's using trigger oscillators can be used if input frequency is as high as the maximum logic clock frequency. The quantization noises of the second‐order DPLL using two trigger oscillators are lower than those of the conventional DPLL. The trigger oscillators can be used in any type of DPLL. Its input frequency becomes higher or its quantization noises become lower.