Abstract
Abstract Accurate alignment between the cavities in cavity-SOI (c-SOI) wafers and lithography on the wafer surface is essential to advanced MEMS production. Existing alignment methods are well defined, but often require specialized equipment or costly software packages available only in professional manufacturing environments. It would be beneficial for the microfabrication world to be able to utilize standard alignment techniques and tools that are easily available also in smaller MEMS fabrication units and especially the majority of research facilities. Therefore, we demonstrate a feasible method for c-SOI wafer alignment using an ASML PAS5500/100 wafer stepper with standard software configuration by relocating ASML alignment markers towards wafer's edges and utilizing a terracing process to reveal them for alignment. Moreover, we characterize the magnitude and behavior of image offset errors that are introduced using this method. The offset error is found to be inversely proportional to the value of the coordinate in each axis, resulting in images being shifted towards the center of the wafer. The measured offset errors are
Highlights
Cavity-SOI (c-SOI) wafers are an emerging form of advanced substrates used in MEMS processing, which feature cavities below the buried oxide (BOX) layer
We demonstrate a feasible method for c-SOI wafer alignment using an ASML PAS5500/100 wafer stepper with standard software configuration by relocating ASML alignment markers towards wafer's edges and utilizing a terracing process to reveal them for alignment
We propose a method that involves patterning ASML alignment markers on the front-side of the handle wafer beneath the BOX layer
Summary
Cavity-SOI (c-SOI) wafers are an emerging form of advanced substrates used in MEMS processing, which feature cavities below the buried oxide (BOX) layer. Buried structures and align them to a pre-fabricated device layer that is bonded on top [10,28] with sub-μm accuracy [29] This method requires specialized equipment, which is not widely accessible, and specialized alignment markers [10,28,29]. It is necessary to define a process whereby alignment to a pre-fabricated c-SOI wafer can be achieved using non-specific front-side alignment markers To this end, a new method is presented using processes commonly used in microfabrication facilities, e.g. a wafer stepper (ASML PAS5500/100) and dry etching, without expensive software- or hardware modifications. We propose a method that involves patterning ASML alignment markers on the front-side of the handle wafer beneath the BOX layer. The alignment is analyzed through the measurement of offsets of the patterned alignment markers
Sign-in/Register to view highlights & summary 
Published Version (
Free)
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call