Abstract
In this paper a basic block of novel topology of multilevel inverter is proposed. The proposed approach significantly requires reduced number of dc voltage sources and power switches to attain maximum number of output voltage levels. By connecting basic blocks in series a cascaded multilevel topology is developed. Each block itself is also a multilevel inverter. Analysis of proposed topology is carried out in symmetric as well as asymmetric operating modes. The topology is investigated through computer simulation using MATLAB/Simulink and validated experimentally on prototype in the laboratory.
Highlights
Multilevel inverter technology has become popular in industry for medium and high voltage applications
The proposed structure uses minimum number of on-state switches and dc sources as compared to topologies presented in literature
A basic block of novel multilevel inverter topology has been proposed in this paper
Summary
Multilevel inverter technology has become popular in industry for medium and high voltage applications. A new type of cascaded modular multilevel inverters (CMMLIs) is presented in [17] It can produce a considerable number of output voltage levels with a reasonable number of components. In [19], a new general multilevel inverter topology based on cascade connection of submultilevel units is presented This topology uses reduced switching components, dc voltage sources, and blocked voltage by switches. A new cascaded seven-level inverter is developed in [21] It uses single dc source and switched capacitor technique. A new symmetric cascade multilevel inverters structure is presented in [23] This structure requires minimum number of power electronic components, gate driver circuits, a power diode, and a dc voltage source.
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