Abstract
Quantum-dot cellular automaton (QCA) is a novel nanotechnology that provides a very different computation platform than traditional CMOS, in which polarization of electrons indicates the digital information. This paper demonstrates designing combinational circuits based on quantum-dot cellular automata (QCA) nanotechnology, which offers a way to implement logic and all interconnections with only one homogeneous layer of cells. In this paper, the authors have proposed a novel design of XOR gate. This model proves designing capabilities of combinational circuits that are compatible with QCA gates within nano-scale. Novel adder circuits such as half adders, full adders, which avoid the fore, mentioned noise paths, crossovers by careful clocking organization, have been proposed. Experiment results show that the performance of proposed designs is more efficient than conventional designs. The modular layouts are verified with the freely available QCA Designer tool.
Highlights
Quantum-dot cellular automaton (QCA) is a new nanotechnology that can help us to achieve low power consumption, high device density, and high clock frequency
How to cite this paper: Ahmad, F., Bhat, G.M. and Ahmad, P.Z. (2014) Novel Adder Circuits Based on Quantum-Dot Cellular Automata (QCA)
The proposed QCA XOR gate and its implementations for half adders and full adders have compared with conventional designs with regards delay, occupied area, and number of used QCA cells
Summary
Quantum-dot cellular automaton (QCA) is a new nanotechnology that can help us to achieve low power consumption, high device density, and high clock frequency. (2014) Novel Adder Circuits Based on Quantum-Dot Cellular Automata (QCA). Utilizing the QCA technology [2] for implementing logic circuits is one of the approaches which, in addition to decreasing the size of logic circuits and increasing the clock frequency and reduces the power consumption of these circuits. A new bitserial QCA adder has been proposed [14], which uses carry feedback and only requires three majority gates and two inverters This bit-serial approach requires a complicated clocking scheme and feedback control. By using Bennett clocking, the power dependence of QCA circuits on the inputs can be effectively removed making it impossible to perform power analysis attack [19]
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