Abstract
This paper presents an ADC architecture comprising a pipelined cyclic ADC and continuous-time delta-sigma ADC; it provides high resolution at medium speed, with small power requirements. It is also reconfigurable for different combinations of speed, precision, and power consumption. The cyclic ADC produces a residue after the final cycle, and the following delta-sigma ADC converts it to a digital value (the residue is then noise-shaped). The ADC output combines the digital outputs of the cyclic ADC and the delta-sigma ADC so as to achieve high resolution. The delta-sigma ADC can be implemented simply with continuous-time analog circuitry. We describe the overall ADC architecture and operation, show simulation results, as well as features such as its potential for reconfiguration and one of ADC architecture candidates with good tradeoff for high resolution, medium speed and small power.
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