A 12 bit, 2-MS/s, 0.016-mm2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator

Abstract

This publication presents a cyclic A/D converter system, which can be used for column-parallel sensor readout applications. The converter system includes ADC, fully integrated ADC references, timing generator, calibration engine, and an on-chip ramp generator for complete on-chip testing. This publication solves the exaggerated issue of feed-forward transient glitches in capacitor-shared cyclic and pipelined ADCs. This publication also solves some existing issues in fully integrated references of pipeline and cyclic ADC, namely reduced voltage range, and memory effects. The area of the core cyclic ADC operating at 12 bit resolution and 2MS/s conversion rate is only 0.016mm2. The measured DNL and INL are +0.47/−0.68 LSB and +/−0.99 LSB respectively. The ADC is implemented in TSMC 55nm CMOS technology using 3.3V devices, the ADC consumes 850µW from 3.3V supply.