Noise-Tolerant Quantum MOS Circuits Using Resonant Tunneling Devices

Abstract

Resonant tunneling devices are promising candidates for comingling with traditional CMOS circuits, yielding better performance in terms of reduced silicon area, faster circuit speeds, lower power consumption, and improved circuit noise margin. These resonant tunneling devices have several intrinsic merits that include: high current density, low intrinsic capacitance, the negative differential resistance effect, and relative ease of fabrication. In this paper, we briefly describe some circuit configurations of Silicon quantum MOS logic family, with a special emphasis on noise-tolerant design that is now becoming an important constraint for robust and reliable operation of very deep submicron VLSI chips. More specifically, we discuss a novel strategy to incorporate quantum-tunneling devices into mainstream dynamic CMOS circuits with a view to improving the noise immunity of the latter. Dynamic CMOS circuits are rampantly used in modern high-performance VLSI chips achieving the best tradeoff between circuit speed, silicon area, and power consumption. However, they are inherently less noise-tolerant than their static CMOS counterparts. With the continuously deteriorating noise margins due to aggressive down scaling of the CMOS fabrication technologies, the performance overhead due to existing remedial noise-tolerant circuit techniques becomes prohibitively high. In this paper, we propose a novel method that utilizes the negative differential resistance property of quantum tunneling devices. The performance and noise immunity of the proposed circuits are evaluated through both analytical studies and SPICE simulations. We demonstrate that the noise tolerance of dynamic CMOS circuits can be greatly improved with very little degradation in circuit speed. The benefit of the proposed technique is evident even for currently available Silicon-based resonant tunneling devices with a relatively small peak-to-valley current ratio.